1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to the metal line layout of memory cells for use within integrated circuits.
2. Description of the Prior Art
It is known to form integrated circuits which at a physical level include polysilicon gate regions and sequences of spaced apart layers of metal lines. The polysilicon gate material is deposited in fingers and is typically used to form the gate material within transistors. The metal lines are used to carry signals and to connect to the other components within the integrated circuit.
Within the integrated circuit as a whole, and particularly as a process geometries are becoming smaller, it is desirable that the polysilicon gate material for the integrated circuit as a whole is laid down in a single direction, i.e. with its long access parallel to a first direction. Similarly, it is desirable that at least the higher level layers of metal lines are laid down in the same direction across both the memory cells and the general purpose logic cells within the integrated circuit. These conditions impose constraints upon memory cell design at the physical level. A further constraint is the desire to provide hierarchical data connections to the memory cells (e.g. through bit lines and then data lines) in order to support banks of memory cells so as to save power and increase speed through the use of shorter and easier to drive lines. Another consideration is that it is normally desirable that metal lines in adjacent layers should be orthogonal to each other so as to reduce the capacitive coupling between those lines.
Conventional memory cells are unable to simultaneously meet the design constraints explained above.